1. Field
This disclosure generally relates to techniques for detecting duplicate requests for a cache line in a level two cache. More specifically, this disclosure relates to techniques for filtering duplicate requests for a cache line in a processor with a level one cache that does not support secondary miss detection.
2. Related Art
High instruction throughput in a processor typically involves rapid translation of virtual addresses and fast memory accesses. To achieve such throughput, the memory subsystem of the processor may include a number of specialized hardware structures, including multiple levels of caches.
During execution, a processor may execute a number of program instructions that access the same cache line (e.g., the same cache entry). If this cache line is not available in a level one (L1) cache, the first miss causes the L1 cache to send a corresponding request to a level two (L2) cache. Upon receiving a second subsequent request for the same cache line, secondary miss detection logic in the L1 cache detects that another request for that cache line is already pending, and ensures that no duplicate requests are sent to the L2 cache for the same cache line.
Unfortunately, providing secondary miss detection in an out-of-order processor can involve substantial additional complexity. For instance, if a number of stalled instructions are waiting for the same cache line, receiving a fill packet at the L1 cache may involve simultaneously writing a large number of registers and activating a large associated set of instructions. Such capabilities may involve substantial additional cost in terms of area, timing, and complexity. Alternatively, not providing secondary miss detection can substantially increase duplicate request traffic for the L2 cache, thereby increasing cache load unnecessarily and reducing processor performance.
Hence, what is needed are techniques for accessing cache data efficiently without the above-described problems of existing techniques.